1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More specifically, the present invention is directed to the techniques that can prevent a crack from occurring in the layers underlying a metal line layer due to the size of the metal line or a space between two adjacent metal line layers.
2. Description of the Related Art
Semiconductor devices generally have a multi-layered structure. When manufacturing such semiconductor devices having a multi-layered structure, only a metal line pattern is inspected, but stresses that are applied to, for example, an insulation layer beneath the metal layer are not considered. Such stresses (e.g., a thermal stress) may cause cracks in one or more layers underlying the metal layer, for example, an insulation layer. As a result, the characteristics of a semiconductor device may deteriorate.
FIG. 1 illustrates a schematic cross-sectional view of a conventional semiconductor device having a multi-layered structure. The semiconductor memory device includes a first insulation layer 12, a resistive layer 13, a second insulation layer 14, a barrier layer 15, and a metal line layer 16, which are sequentially formed on a substrate 11.
In the semiconductor device having such a multi-layered structure of FIG. 1, when a subsequent annealing process is performed after forming the metal line layer 16, the stress structure is changed. In other words, due to a thermal stress, the stress direction in one or more of the layers 13 to 16 is changed as shown in FIGS. 2A and 2B. FIG. 2A illustrates a cross-sectional view of a stress direction before an annealing process is performed, and FIG. 2B illustrates a cross-sectional view of a stress direction in underlying layers after an annealing process is performed. In FIGS. 2A and 2B, the arrows denote the stress direction.
As the direction of a stress is changed, the stress is accumulated and, thus, a crack 17 may occur in a portion of the second insulation layer 14 corresponding to a gap in the metal line layer 16 as shown in FIG. 1. FIGS. 4A to 4D are photographs illustrating cracks that occur due to a stress in the conventional semiconductor device. Furthermore, when a crack is deepened, as shown in FIGS. 3A and 3B, the resistive layer 13 may be destroyed, thereby causing a low reliability. FIGS. 3A and 3B are photographs illustrating a crack that occurs in the resistive layer 13.
Japanese Patent Publication No. 10-84059 describes a technique that relaxes the concentration of stress on the peripheral edge of a metal board to prevent an underlying ceramic board from deteriorating in mechanical strength and to protect it against cracking. In this technique a groove is provided inside the peripheral edge of one of the surfaces of the metal plate whose other surface is bonded to a high-thermal conductivity silicon nitride board (ceramic board).
U.S. Pat. No. 5,229,642 describes a technique that forms slits or rows of small holes in corner portions of a guard ring to prevent a passivation film on the guard ring from being cracked by stresses caused by a resin mold package concentrating in the four corners of the semiconductor substrate.
However, the prior art as described above does not suggest a technique that prevents a crack from occurring in one or more layers underlying the metal line layer due to the size of the metal line or a gap between two adjacent metal line layers.